Integrated circuits (ICs) typically include a plurality of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs) or MOS transistors, over a semiconductor substrate and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate in the metallization layers and conductive vias run perpendicular to the substrate between the metallization layers to selectively interconnect the metal lines.
Magnetoresistive random-access memory (MRAM) is a non-volatile random-access memory technology that can be incorporated into ICs and has been under development since the 1990s. A typical MRAM device stores data by means of magnetic storage elements, not in electrical charge or current. The storage elements are formed from two ferromagnetic plates, each of which can hold a magnetic field. The ferromagnetic plates are separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity, and the other plate's field can be changed to match an external field to store memory.
One kind of MRAM stores data in a magnetic tunnel junction (MTJ) that is configured as a layered memory stack (MTJ stack). The MTJ stack has two magnetic films, that is, a pinned layer and a free layer. The magnetization direction of the pinned layer is fixed while the magnetization direction of the free layer can rotate freely for storing information. There is an insulating layer between the pinned layer and a free layer.
MTJ stacks are often inserted into the BEOL of a complementary MOS (CMOS) process. FIG. 1 illustrates an IC 2 that includes a MTJ stack 4 that is arranged in an interlayer dielectric (ILD) layer or layers 6 of dielectric material(s) of a BEOL interconnect structure 8 above a semiconductor substrate 10. The MTJ stack 4 includes a pinned layer 12, a free layer 14, and an interposing insulating layer 16 and is formed on top of a distal end portion 17 of an extended bottom electrode 18. At its proximal end portion 19, the extended bottom electrode 18 is electrically coupled to a MOS transistor 20 by a conductive stud 22 that includes one or more axially aligned (e.g., vertically aligned) vias and/or metal interconnects 24 that together form a conductive column structure. Also shown in FIG. 1 are metal lines 26 and 28 (e.g., bit and word lines, respectively) that may be formed independently along separate but parallel metallization layers.
Currently, the extended bottom electrode 18 may include various materials, such as, for example, a tantalum nitride/tantalum stack that forms a bi-layer extended bottom electrode. This bi-layer extended bottom electrode has some potential issues however for MRAM applications such as having relatively high resistance, which in turn affects the MRAM electrical performance. Thus, a major challenge for making a successful MRAM is how to integrate a bottom electrode with an overlying MTJ stack within a CMOS BEOL process. To improve electrical performance, a bottom electrode with relatively low sheet resistance and low contact resistance with the underlying metal interconnect of the conductive stud and the overlying MTJ stack is desirable.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) with improved electrical performance of a bottom electrode with a metal interconnect and a MTJ stack, and integrated circuits formed by such methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.